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Careers at TeraSilicon IQ
Build Your Engineering Career in Formal Verification and Static Timing Analysis.
We welcome engineers interested in digital design, formal methods, SystemVerilog, assertion development, timing analysis and semiconductor engineering.
Primary domain
Formal Verification Engineering
Skills we look for:
- Digital design fundamentals
- Verilog / SystemVerilog
- SystemVerilog Assertions (SVA)
- Formal property development
- Proof debugging
- Verification methodology
Supporting capability
Synthesis, LEC and STA Engineering
Skills we look for:
- Digital fundamentals
- Timing concepts
- Setup and hold
- Clock concepts
- SDC
- Timing reports and STA methodology
Express your interest
Share your details and a link to your resume or LinkedIn profile. We review applications against current requirements and contact shortlisted engineers.
Submitting an application does not guarantee an interview or a role. Openings, terms and compensation are confirmed only in a formal written offer.
You can also email your resume to careers@terasiliconiq.com.